1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device allowing electrical data writing and data erasing.
2. Description of the Background Art
As performance of a microprocessor or the like is enhanced, a demand for both a larger capacity and a higher speed in a non-volatile memory allowing electrical data writing and data erasing has become intense.
Accordingly, a number of non-volatile memories aiming at higher data transfer rate have conventionally been proposed, as described in Japanese Patent Laying-Open No. 2000-100186, and “A 1-Mbit CMOS EPROM with Enhanced Verification”, Roberto Gastaldi et al., IEEE Journal of SOLID-STATE CIRCUITS, Vol. 23, No. Oct. 5, 1988, for example.
For example, a non-volatile memory described in Japanese Patent Laying-Open No. 2000-100186 achieves higher speed in data reading in the following manner. That is, a feedback signal is varied during a period for precharging a bit line and a reference bit line connected to a reference memory cell and during a period for sensing a potential difference between a selected bit line and the reference bit line. In this manner, an amount of charge supply to a bit line in precharging the same can be set to any level, and a loss in charge supply such as overprecharge of the bit line can be minimized.
Here, in a conventionally proposed non-volatile memory, a plurality of bit lines are provided, whereas a single reference bit line connected to a reference memory cell is generally provided.
Therefore, a period for precharging the reference bit line to a prescribed potential is necessary after a sensing operation in data reading, and next data reading is performed after the precharge period.
On the other hand, when data is successively output for each reading cycle such as in data reading in a burst mode, the precharge period imposes restriction on the data transfer rate. In other words, the non-volatile memory with such a configuration requires a sufficient precharge period before a sensing period.
This is a key factor inhibiting higher data transfer rate in the non-volatile memory in which higher integration is demanded, because the precharge period is extended with an increase in the number of memory cells connected to a bit line.